- Decrements the accumulate value at each false to true transition and retains the accumulated value when the instruction goes false or when power cycle occurs.
- The CTD is an instruction that counts false to true transition. When this transition happen the accumulated value is decrements by one count.
- A CTD accumulation is reset by the RES instruction.
- If the accumulation value is below the minimum range then the underflow (UN) bit will be true.
- Resets the accumulated value and status bit of a timer or counter.
- Use a RES instruction to reset timers or counters. When the RES instruction is enabled, it resets the Timer On Delay, Retentive Timer, and Counter Up, Counter Down instruction having the same address as the RES instruction.
Example 1
We want to have a count down on an input signal. Once we reach a count of 0 we will energize a light. When a button is pressed then count will be reset.
Input / Output
- Input I:1.0/0
- Light O:2.0/0
- Button I:1.0/1
Ladder Logic Solution
When Input goes from off to on the counter Acc value will decrement by 1. When the Acc > = Preset then the bit done will be true; hence the light will go on.
When Input goes on the counter Acc value will decrement by 1. When the Acc < Preset then the bit done will be false, hence the light will go off.
When the button is pressed this will energize the rung for only one scan and so resetting the counter. This will reset the Acc value to 0.
Note
- When the done bit of the counter goes on the counter will keep counting. Therefore if the input keeps going from false to true at one point we will get an underflow bit on.
- If the accumulation value is below the minimum range then the underflow (UN) bit will be true.
