

Double Division Instruction in Ladder Logic 
DDV  Double DivisionWhen rung conditions are true, this output instruction divides the contents of the math register (S:13 and S:14), containing 32 bits of data, by the source (16 bits of data) and stores the result in the destination and the math register. ExampleEquation: N7:72 = N7:70 * N7:71 (30000 * 1000 = 60000) Notice that the result of this multiplication will not fit in N7:72(16 bit), but the math register (32) will be able to hold on to this value. So if we look at the value of N7:72 = 5536. Ladder Logic SolutionNow lets have a look at the value held in the math register. The value is 60000, which is a valid result. Now we can use this value with the DDV instruction. Next we want to divide the value held in the math register in 6. The DDV instruction will take the value from the math register directly and divided it by 6. Now the result of this division could be held in N7:74. NoteUpon execution the unrounded quotient is placed in the most significant word of the math register. The remainder is placed in the least significant word of the math register. If the result of the DDV is > 32767 or < 32768 then a minor fault will be generated. 
