

Arithmetic Instructions in Ladder Logic 
IntroductionBasic Ladder Logic instructions allow very simple logical decisions. Arithmetic Ladder Logic instructions go beyond the simple true or false operation to give the ability to more complex operations. It retrieves one or more value, perform an operation and store the result in memory. Status FileThere is a very close relation between math instruction and some of the control status bits. After a math instruction is executed, the arithmetic status bits in the control status file are updated. Control status file is the data file "S2  Status".
DefinitionThe following is a list of the comparison instructions in SLC 500: ADD  AddingSymbolDefinitionWhen rung conditions are true, this output instruction adds Source A to Source B and stores the result at the destination address. Source A and Source B can either be values or addresses that contain values, however Source A and Source B cannot both be constants.
SUB  SubtractSymbolDefinitionWhen rung conditions are true, the SUB output instruction subtracts Source B from Source A and stores the result in the destination. Source A and Source B can either be values or addresses that contain values, however Source A and Source B cannot both be constants.
MUL  MultiplySymbolDefinitionUse the MUL instruction to multiply one value (source A) by another (source B) and place the result in the destination. Source A and Source B can either be constant values or addresses that contain values, however Source A and Source B cannot both be constants. The math register contains the 32bit signed integer result of the multiply operation. This result is valid at overflow.
DIV  DivideSymbolDefinitionWhen rung condition is true, this output instruction divides Source A by Source B and stores the result in the destination and the math register. The value stored in the destination is rounded. The value stored in the math register consists of the unrounded quotient (placed in the most significant word) and the remainder (placed in the least significant word). Source A and Source B can either be constant values or addresses that contain values, however Source and Source B cannot both be constants.
DDV  Double DivideSymbolDefinitionWhen rung conditions are true, this output instruction divides the contents of the math register (S:13 and S:14), containing 32 bits of data, by the source (16 bits of data) and stores the result in the destination and the math register. The math register initially contains the dividend of the DDV operation. Upon execution the unrounded quotient is placed in the most significant word of the math register. The remainder is placed in the least significant word of the math register.

